A differential amplifier circuit is used to compare two signals for detecting a differential signal or to offset the noise of two simultaneously input signals, and is a circuit used in electronic devices. A balanced differential amplifier employs a need based strategy of matching the two branches of the differential pair (desire is to have minimum offset). In the case of balanced differential amplifier, noise that is generated due to high capacitances is cancelled out. In conventional unbalanced difference amplifiers, one of the differential input nodes is coupled to a reference node and the other is coupled to a signal source. The reference may not be in synchronization with the actual charge feeding or sinking of the branch coupled to the signal source. This creates additional offset over and above the offset introduced by asymmetric devices. Thus, a conventional unbalanced amplifier may be highly susceptible to failures due to mismatches between the differential branches feeding it.
FIG. 1 illustrates a circuit diagram 100 of a conventional biasing circuit. The circuit 100 includes a core block 102, pre-charge modules, such as 104A, 104B and 104C, a multiplexer module 106, a latch circuit 108, and two PMOS pass transistors 110 and 112 coupled to the latch nodes SAT and SAF. In one embodiment, the core block 102 can be a NAND block, where input non-differential signals are allowed to enter a branch. The pre-charge modules 104A, 104B and 104C include PMOS transistors. The latch circuit 108 includes two PMOS transistors 114 and 116 and two NMOS transistors 118 and 120. The transistors 114 and 118 and the transistors 116 and 120 are individually coupled to form two inverters.
The two inverters are cross coupled to form the latch circuit 108. A pull down transistor 122 is coupled to the latch circuit 108. A drain terminal of the pull down transistor 122 is coupled to the source terminals of the NMOS transistors 118 and 120 and the source terminal is coupled to a ground terminal. The gate terminal is controlled by a control signal SON. A source terminal of the PMOS pass transistor 110 is coupled to a node NET A, a drain terminal is coupled to a latch output node SAT, and the gate terminal is controlled by the control signal SON. A source terminal of the PMOS pass transistor 112 is coupled to a node NET B, a drain terminal is coupled to a latch output node SAF, and the gate terminal is controlled by the control signal SON.
A non-differential input signal may enter the branch, when a clock signal CK is enabled. The non-differential input signal is multiplexed and is passed onto the latch output node SAT through the PMOS transistor 110. A reference signal is given to the latch output node SAF through the PMOS transistor 112. The non-differential signals are read in three phases. First, the branches, the reference line and latch output nodes SAT and SAF are pre-charged before a read or resolving cycle. Second, when the control signal CK is enabled, the pre-charge circuits are turned off, as their inputs go high. However, the reference pre-charge will not be turned off. It is in an on state. One of multiplexer pass transistors is turned on (i.e., its input turns low) depending on the multiplexer address, and the input signal gets coupled to the latch output node SAT or SAF. A control signal SON is turned high and the pull down transistor is turned on and latch output nodes are decoupled from the external signal. The sense amplifier resolves the initial difference created between SAT and SAF.
However, due to the inherent mismatch in the devices coupled to the differential branches, the conventional method presents several problems at different stages of manufacturing as well as in the circuitry or architecture, where the non-differential amplifier is employed. It suffers from active and poly masking problems like STI (Shallow Trench Isolation) matching, mask misalignment, doping gradient and poly shadowing. It suffers from device level problems like large figure size, gate/drain/metal capacitance mismatches and physical effects like individual signal and supply capacitance differences, charge feed through internal node capacitance, and pass transistor shared node capacitance differences between the differential nodes.
Therefore, there is a need for a sensing scheme for a low swing non-differential signal with a low input referred offset, so that the robustness of the system is improved.